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TE CH
T224162B
DRAM
256K x 16 DYNAMIC RAM
EDO PAGE MODE
FEATURES
* Industry-standard x 16 pinouts and timing functions. * Single 5V (10%) power supply. * All device pins are TTL- compatible. * 512-cycle refresh in 8ms. * Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN. * Extended data-out (EDO) PAGE MODE access cycle. * BYTE WRITE and BYTE READ access cycles.
PIN ASSIGNMENT ( Top View )
Vcc I/01 I/02 I/03 I/04 Vcc I/05 I/06 I/07 I/08 1 2 3 4 5 6 7 8 9 10 TSOP(II) NC NC 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 NC CASL CASH OE A8 A7 A6 A5 A4 VSS 40 39 38 37 36 35 34 33 32 31 Vss I/016 I/015 I/014 I/013 Vss I/012 I/011 I/010 I/09
OPTION
TIMING
22ns 25ns 28ns 35ns 45ns 50ns
EDO
125 MHz 100 MHz 100 MHz 83 MHz 60 MHz 50 MHz MARKING J S
MARKING
-22 -25 -28 -35 -45 -50
WE RAS NC A0 A1 A2 A3 Vcc
PACKAGE
SOJ TSOP(II)
GENERAL DESCRIPTION
The T224162B is a randomly accessed solid state memory containing 4,194,304 bits organized in a x16 configuration. The T224162B has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. It offers Fast Page mode with Extended Data Output. The T224162B CAS function and timing are determined by the first CAS to transition low and by the last to transition back high. Use only one of the two CAS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL transiting low in a WRITE cycle will write data into the lower byte (IO1~IO8), and CASH transiting low will write data into the upper byte (IO9~16). Taiwan Memory Technology, Inc. reserves the right P. 1 to change products or specifications without notice.
Vcc I/01 I/02 I/03 I/04 Vcc I/05 I/06 I/07 I/08 NC NC WE RAS NC A0 A1 A2 A3 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SOJ
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vss I/016 I/015 I/014 I/013 Vss I/012 I/011 I/010 I/09 NC CASL CASH OE A8 A7 A6 A5 A4 VSS
Publication Date: AUG. 2000 Revision:L
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T224162B
FUNCTIONAL BLOCK DIAGRAM
WE CASL CASH
CAS
CONTROL LOGIC
DATA-IN BUFFER DQ01 16
. .
DQ16
NO.2 CLOCK GENERATOR DATA-OUT BUFFER 9 COLUMN. ADDRESS BUFFER 9 COLUMN DECODER
OE
16
A0 A1 A2 A3 A4 A5 A6 A7 A8 9 9 ROW DECODER ROW. ADDRESS BUFFERS(9) REFRESH COUNTER REFRESH CONTROLLER
512 8 SENSE AMPLIFIERS VO GATING 512 x 16 8
9
512
512 x 512 x 16 MEMORY ARRAY
RAS
NO.1 CLOCK GENERATOR
Vcc Vss
PIN DESCRIPTIONS
PIN NO. 16~19,22~26 14 28 29 13 27 2~5,6~10,31~34,36~39 1,6,20 21,35,40 11,12,15,30 SYM. A0-A8 RAS
CASH
TYPE Input Input Input Input Input Input Supply Ground Address Input
DESCRIPTION Row Address Strobe Column Address Strobe /Upper Byte Control Column Address Strobe /Lower Byte Control Write Enable Output Enable Power, 5V Ground No Connect
CASL WE OE I/O1 - I/O16 Vcc Vss NC
Input/ Output Data Input/ Output
Taiwan Memory Technology, Inc. reserves the right P. 2 to change products or specifications without notice.
Publication Date:AUG. 2000 Revision:L
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T224162B
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS..... -1V to +7V Operating Temperature, Ta (ambient) ..0C to +70 C Storage Temperature (plastic)........ -55C to +150C Power Dissipation .......................................... Short Circuit Output Current......................... 50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0C Ta 70C; VCC = 5V 10 % unless otherwise noted) DESCRIPTION CONDITIONS Supply Voltage Supply Voltage Input High (Logic) voltage Input Low (Logic) voltage Input Leakage Current 0V VIN 7V 0V VOUT 7V Output Leakage Current Output(s) disabled Output High Voltage IOH = -5 mA Output Low Voltage IOL = 4.2 mA Note: 1.All Voltages referenced to Vss MAX DESCRIPTION Operating Current CONDITIONS SYM. -22 -25 -28 -35 -45 -50 UNITS NOTES tRC = min Icc1 190 180 170 150 130 110 mA 1,2 RAS , CAS cycling , TTL interface, RAS , CAS =VIH, DOUT=High-Z CMOS interface, RAS , CAS > Vcc-0.2V RAS -only refresh Current Standby Current
CAS Before RAS Refresh Current
SYM. Vcc Vss V IH V IL ILI ILO VOH VOL
MIN 4.5 0 2.4 -1.0 -10 -10 2.4 0
MAX 5.5 0 Vcc+1 0.8 10 10 Vcc 0.4
UNITS V V V V uA uA V V
NOTES 1 1 1
4 Icc2 2
4 2
4 2
4 2
4 2
4 2
mA mA 2 1
Standby Current
tRC = min RAS =VIH, CAS =VIL tRC = min
Icc3 190 180 170 150 130 110 mA Icc5 5 5 5 5 5 5 mA
Icc6 190 180 170 150 130 110 mA Icc7 190 180 170 150 130 110 mA 1,3
EDO Page Mode Current tPC = min
Note: 1. Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Taiwan Memory Technology, Inc. reserves the right P. 3 to change products or specifications without notice. Publication Date: AUG. 2000 Revision:L
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T224162B
CAPACITANCE
(Ta =25C, Vcc =5V 10 %) Parameter Input Capacitance (address) Input Capacitance (clocks) Output Capacitance (data-in, data-out) Symbol CI1 CI2 CI/O Typ Max 5 7 10 Unit pF pF pF Notes 1 1 1
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
AC ELECTRICAL CHARACTERISTICS (note 14)
(Ta =0 to 70C, Vcc=5V 10 %, Vss=0V) Test Conditions (note 29) AC CHARACTERISTICS PARAMETER Read or Write Cycle Time Read Write Cycle Time EDO-Page-Mode Read or Write Cycle Time EDO-Page-Mode ReadWrite Cycle Time Access Time From RAS Access Time From CAS
SYM t RC -22 42 45 65 10 32 22 7 8 11 13 22 10K 25 25 7 8 12 14 10K 28
Input timing reference levels: 0.8V, 2.4V Output Load: 2TTL gate + CL (50pF)
-25 -28 48 70 10 34 28 7 8 13 15 10K 35 65 95 12 40 35 9 9 15 18 10K 45 -35 85 115 16 46 45 11 11 19 22 10K 50 -45 -50 100 135 20 57
UNIT Notes
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
t RWC 62 t PC t PCM t RAC t CAC 8 30
ns ns ns ns 50 13 13 23 26
10K
22 22 4 5,20 13,20
ns ns ns ns ns ns
t OAC Access Time From OE Access Time From Column t AA Address
Access Time From CAS Precharge
RAS Pulse Width
t ACP t RAS
20
RAS Pulse Width (EDO Page Mode) RAS Hold Time RAS Precharge Time CAS Pulse Width CAS Hold Time CAS Precharge Time (EDO Page Mode) CAS to RAS Precharge Time
t RASC 22 100K 25 100K 28 100K 35 100K 45 100K 50 100K ns t RSH t RP t CAS t CSH t CP 7 15 4 19 3 9 3 15 10K 7 15 4 20 3 10 3 17 10K 7 17 4 22 3 10 3 19 10K 9 25 4 30 3 10 3 26 10K 11 35 6 40 5 10 5 34 10K 13 37 8 50 6 19 5 37 10K
ns ns ns ns ns ns ns
27 26 19 23 7,18 19
RAS to CAS Delay Time t RCD
t CRP
Taiwan Memory Technology, Inc. reserves the right P. 4 to change products or specifications without notice.
Publication Date:AUG. 2000 Revision:L
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T224162B
-22 0 5 8 0 4 17 11 0 0 0 3 3 8 0 4 19 4 6 5 0 4 19 0 4 19 4 6 5 0 4 19 34 11 0 5 8 0 4 19 12 0 0 0 3 3 8 0 4 21 4 6 5 0 4 21 37 12 -25 0 5 8 0 4 21 13 0 0 0 3 3 8 0 4 30 4 7 7 0 4 30 51 13 -28 0 5 8 0 4 30 15 0 0 0 3 3 15 8 0 6 46 6 9 9 0 6 40 61 20 -35 0 5 8 0 6 40 19 0 0 0 3 3 15 8 0 7 51 8 10 11 0 7 45 70 26 -45 - 50 0 5 10 0 7 45 23 0 0 0 3 3 15 8 29
AC ELECTRICAL CHARACTERISTICS (continued)
AC CHARACTERISTICS PARAMETER Row Address Setup Time Row Address Hold Time
SYM t ASR t RAH
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
UNIT Notes ns ns ns ns
RAS to Column Address t RAD Delay Time Column Address Setup Time t ASC Column Address Hold Time t CAH Column Address Hold Time t AR (Reference to RAS ) Column Address to RAS t RAL Lead Time Read Command Setup Time t RCS Read Command Hold Time t RCH Reference to CAS
8
18 ns 18
ns ns
15,18 9,15, ns 19
ns ns ns ns ns ns
Read Command Hold Time Reference to RAS CAS to Output in Low-Z Output Buffer Turn-off Delay From CAS or RAS Output Buffer Turn-off to OE
t RRH t CLZ t OFF1 t OFF2
9 20 10,17, 20 17,28
Write Command Setup Time t WCS Write Command Hold Time Write Command Hold Time (Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS ) RAS to WE Delay Time
t WCH t WCR tW P t RWL t CW L t DS t DH t DHR
11,15, 18 ns 15,27 15
ns ns ns ns ns
15 15 15,19
12,20 ns 12,20
ns ns
t RWD 31
11
AC ELECTRICAL CHARACTERISTICS (continued)
Taiwan Memory Technology, Inc. reserves the right P. 5 to change products or specifications without notice. Publication Date:AUG. 2000 Revision:L
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SYM t AWD t CWD tT t REF t RPC t CSR t CHR -22 -25 -28 -35 -45
T224162B
-50
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
AC CHARACTERISTICS PARAMETER Column Address to WE Delay Time CAS to WE Delay Time Transition Time (rise or fall) Refresh Period (512 cycles) RAS to CAS Precharge Time CAS Setup Time (CBR REFRESH) CAS Hold Time (CBR REFRESH) OE Hold Time From WE During Read-Modify-Write Cycle OE Low to CAS High Setup Time OE High Hold Time From CAS High OE High Pulse Width OE Setup Prior to CAS During Hidden Refresh Cycle Last CAS Going Low to First CAS Returning High Data Output Hold After CAS Returning Low Output Disable Delay From WE
UNIT Notes
21 17 1.5 50 8
21 17 1.5 50 8
24 18 1.5 50 8
31 25 2.5 50 8
35 27 2.5 50 8
43 33 2.5
ns 11 ns 11,18 ns 2,3 ms ns ns 1,18 ns 1,19 ns 16 ns ns ns ns
50 8
10 5 7
10 5 7
10 5 7
10 10 10
10 10 10
10 10 10
t OEH
4
4
4
4
6
8
t OES t OEHC t OEP t ORD
4
4
4
4
5
5
2 2 0
2 2 0
2 2 0
2 2 0
2 2 0
2 2 0
t CLCH t COH t WHZ
4 3 3 6
4 3 3 7
4 3 3 7
4 3 3 7
6 4 3 7
8 5 3
ns ns 9 ns
21
Taiwan Memory Technology, Inc. reserves the right P. 6 to change products or specifications without notice.
Publication Date:AUG. 2000 Revision:L
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TE CH
T224162B
goes low result in a LATE WRITE( OE controlled) cycle. 12. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY-WRITE operation is not possible. 14. An initial pause of 100ms is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 15. WRITE command is defined as WE going low. 16. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 17. The I/Os open during READ cycles once tOFF1 or tOFF2 occur. 18. The first CAS edge to transition low. 19. The last CAS edge to transition high. 20. Output parameter (I/O) is referenced to corresponding CAS input, IO1~8 by CASL and IO9~16 by CASH . 21. Last falling CAS edge to first rising CAS edge. 22. Last rising CAS edge to next cycle's last rising CAS edge. 23. Last rising CAS edge to first falling CAS edge. 24. First IOs controlled by the first CAS to go low. 25. Last IOs controlled by the last CAS to go high. 26. Each CAS must meet minimum pulse width. 27. Last CAS to go low. 28. All IOs controlled, regardless CASL and CASH . 29. Data outputs are measured with a load of 50pF. The output reference levels are VOH /VOL =2.0V/0.8V; The input levels are VIH/VIL= 3.0V/0V. Publication Date:AUG. 2000 Revision:L
Notes: 1. Enables on-chip refresh and address counters. 2. V IH(2.4V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between VIH (2.4V) and VIL (0.8V). 3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. 4. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that t RCD exceeds the value shown. 5. Assume that tRCD tRCD(max) . 6. If CAS is low at the falling edge of RAS , data-out will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS and RAS must be pulsed high. 7. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, access time is controlled by tCAC. 8. Operation within the t AD limit ensures that R tRAC(max) can be met. tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, access time is controlled by t AA. 9. Either tRCH or tRRH must be satisfied for a READ cycle. 10. tOFF1 (max) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 11. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycles only. If t CS tWCS(min), the cycle is an W EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD(min), tAWD tAWD (min) and tCWD tCWD(min), the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held high and WE taken low after CAS
Taiwan Memory Technology, Inc. reserves the right P. 7 to change products or specifications without notice.
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READ CYCLE
t RC tR A S tR P
T224162B
V RAS V IH IL
tCRP CA S L , CA S H V IH V IL tR A D tA S R ADDR V IH V IL ROW tRAH
tR C D
tC S H tR S H tC A S
tC L C H
tR R H
tAR tR A L t AS C tC A H C O L U MN t RC S tR C H ROW
V WE V IH IL
tA A tR A C tC A C tC L Z N O TE 1 t OFF 1
I/O
V OH V OL
O P EN tO A C
V A L ID D A T A tO F F 2
OP EN
V OE V IH IL
EARLY WRITE CYCLE
tR C tR A S RAS V IH V IL tR P
tC R P V CA S L ,C AS H V IH IL t R AD
tR C D
tC S H tR S H tC A S
tC L C H
tAR tA S R tRAH RO W t AS C tR A L tC A H ROW
A DDR
V IH V IL
C O L U MN t C WL t R WL t WC R t WC S t WC H t WP
WE
V IH V IL tD S
tD H R tD H V A L ID D A T A
V IOH I/O V IOL OE V IH V IL
DON'T CARE UNDEFINED
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. Taiwan Memory Technology, Inc. reserves the right P. 8 to change products or specifications without notice. Publication Date: AUG. 2000 Revision:L
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READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t R WC tR A S RAS V IH V IL tR P
T224162B
tC R P CA S L ,C AS H V IH V IL
tR CD
tC S H tR S H tC A S
tCLCH
tA R tR A D tA S R tR A H ROW t AS C tR A L tC A H RO W t R WD t C WD t A WD t C WL t R WL t WP
A DDR V IH V IL
COLUMN t RC S
V IH WE V IL
tA A tR A C tC A C t CL Z tD S
VA L ID D
t DH OPE N
V I/O IOH V IOL V IH V IL
OP EN tO A C
OU T
V A L ID D
IN
tO F F 2
tO E H
OE
EDO-PAGE-MODE READ CYCLE
t R A SC tR P
V RAS VIH IL
t CR P
tC S H t RC D tC A S , tC L C H
tP C tC P
( NO T E 2 ) tC AS , tC L C H
t CP
tR S H tC AS , tC L C H
tC P N
CA S L, CA S H
VIH V IL
tR A D tR A H
tAR tR A L t AS C tC A H tA S C tC A H tA S C tC A H tA S R
ADDR
VIH V IL
RO W t RC S
C OLUMN
C O L U MN
C OLUMN tR C H
ROW t R RH
WE VIH V IL
t AA tR A C tC A C tCLZ tC O H V A L ID DA TA tO A C tO E S
tA A tA C P tC A C tC L Z V A L ID D AT A tO FF 2
t AA tA C P tC A C N OTE1 tO F F 1 V A L ID DA TA tO F F 2 OP EN
I/O
V OH V OL
OP EN
tO E H C
tO A C tO E S
OE
VIH V IL
tOEP
DON'T CARE UNDEF INED
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of RAS . Both measurements must meet the t PC specification. Taiwan Memory Technology, Inc. reserves the right P. 9 to change products or specifications without notice. Publication Date: AUG. 2000 Revision:L
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EDO-PAGE-MODE EARLY-WRITE CYCLE
t R A SC
T224162B
t RP
RAS
VIH V IL
tC R P
tC S H tRC D t CA S , tC L C H
tP C tC P tC A S , t C L C H t CP
tR S H tC A S , tC LC H
tC P N
V IH CAS L ,C AS H V IL
tAR tR A D t AS R tR A H tA S C tC A H tA S C t C AH tA S C tR A L tC A H
ADDR
V IH V IL
RO W
C O L U MN tW C S tC W L tW C H tW P
C OLUMN tWC S tC W L tW C H tW P
C O LU M N tW C S tC W L tW C H tWP
ROW
WE V IH V IL
tW C R tD H R tD S tD H tD S tD H tD S t RWL tD H
V IOH I/O V IOL V IH V IL
V A L ID D A T A
V A L ID D A T A
V A L ID D A T A
OE
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t R AS C tR P
RA S V IH V IL
tC RP t RC D
tC S H tC A S , tC L C H t CP
tP C M tC A S , tC L C H
tC P
t RS H tC A S , tC LC H
tC P N
V CA S L ,C AS H V IH IL
tA SR
tA R tR A D tR A H
tR A L tA S C tC A H t AS C tC A H tA S C tC A H
ADDR V IH V IL
ROW
C O L U MN tRW D tRC S tC W L tW P tA W D tC W D
C O L U MN
C O L U MN
RO W t RW L
tC W L tW P tA W D tC W D
tA W D tC W D
tC W L tW P
WE V IH V IL
tR A C
t AA tD H tD S tC A C tC L Z
tA A tD H t AC P tC A C tC L Z
VAL I D D OU T VA LI D D IN VAL I D DO U T VA LI D D IN
tA A tA C P tC A C tC L Z
VAL I D DO U T VAL I D D IN
tD H tD S
tD S
I/O
V IOH V IOL
OP EN
O PEN
tO F F 2 tO A C tO A C
tOFF2 tO A C
tOFF2 tO E H
V OE V IH IL
DON'T CAR E UNDEF INED
Note: 1. tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 10 Publication Date: AUG. 2000 Revision:L
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RA S V IH V IL
TE CH
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE)
t R A SC
T224162B
tR P
tCSH tC R P tR C D t PC tCAS tC P tC A S t PC tCP tR S H tC A S tC P
V C AS V IH IL t R AD tA S R t R A H V ADDR V IH IL ROW
tAR tA S C tC A H tA S C tC A H tA S C
tR A L tCAH RO W
C O L U M N (A) tRCS
C O LU M N(B ) tRCH
C O L U M N (N ) t WC S t WC H
WE V IH V IL tR A C
tA A tCAC
tA A t AC P tC A C tC O H VA L ID D A TA (A) t OA C V A L ID D A T A (B )
VALID DATA IN
t WH Z
tD S
t DH
V IOH I/O V IOL
OP EN
OE
V IH V IL
RAS ONLY REFRESH CYCLE (ADDR=A0-A8 ; OE , W E =DON`T CARE)
tR C tR A S V IH R AS V IL tR P
tC R P
t RP C
V CA S L ,C A S H V IH IL
tA S R RO W
tRAH ROW
A DDR
V IH V IL
V I/O V OH OL
OP EN
DON'T CARE UNDEFINE D
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 11
Publication Date: AUG. 2000 Revision:L
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RA S
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CBR REFRESH CYCLE (A0-A8 ; OE =DON`T CARE)
T224162B
tR P V IH V IL
tR A S
tRP
tR A S
tR P C tC P N tC S R t C HR t RP C tC S R tC H R
V C A S H, CA S L V IH IL I/O WE V IH V IL O P EN
HIDDEN REFRESH CYCLE ( W E =HIGH ; OE =LOW)
(R EA D ) tRAS R AS V IH V IL tRP (R E F R E S H ) tR A S
tCRP
tR C D
t R SH
t C HR
C AS L ,C A S H
V IH V IL tR A D tA S R tR A H R OW
tA R tRAL tA S C tCAH
V ADDR V IH IL
C O L U MN tA A tR A C tC A C tCLZ NOT E1 tO F F 1
I/O
V OH V OL
O P EN t OA C
V A L ID D A T A tO F F 2
O P EN
OE
V IH V IL
t ORD
DON'T CARE UNDEFINED
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
Taiwan Memory Technology, Inc. reserves the right P. 12 to change products or specifications without notice.
Publication Date: AUG. 2000 Revision:L
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T224162B
PACKAGE DIMENSIONS 40-LEAD SOJ DRAM (400 mil)
SYMBOL A B C D E F G H I J K L y
DIMENSIONS IN INCHES 1.025 0.010 0.400 0.005 0.045(MAX) 0.050 0.006 0.019 0.003 0.026 0.003 0.440 0.010 0.011 0.003 0.025(MIN) 0.364 0.020 0.047 0.006 0.150(MAX) 0.004(MAX)
DIMENSIONS IN MM 26.0350.254 10.1600.127 1.143(MAX) 1.27 0.152 0.483 0.08 0.661 0.080 11.1760.254 0.280 0.080 0.635(MIN) 9.246 0.508 1.194 0.152 3.810(MAX) 0.102(MAX)
Taiwan Memory Technology, Inc. reserves the right P. 13 to change products or specifications without notice.
Publication Date: AUG. 2000 Revision:L
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TE CH
T224162B
PACKAGE DIMENSIONS 40-LEAD TSOP II DRAM (400 mil)
"A"
SYMBOL A A1 A2 b e D E E1 L1' L' y
DIMENSIONS IN INCHES 0.047(max) 0.0040.002 0.0390.002 0.014(typ.) 0.030(typ.) 0.7250.004 0.4630.008 0.4000.004 0.031 0.0200.004 0.004(max) 0~5
DIMENSIONS IN MM 1.20(max) 0.100.05 1.000.05 0.35(typ.) 0.80(typ.) 18.410.10 11.760.20 10.160.10 0.80 0.5000.10 0.10(max) 0~5
Taiwan Memory Technology, Inc. reserves the right P. 14 to change products or specifications without notice.
Publication Date: AUG. 2000 Revision:L

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